Bipolar transistor

ABSTRACT

The present invention relates to a hetero-bipolar transistor. This transistor comprises a semi-insulating InP substrate, a buffer layer on the substrate, a sub-collector layer on the buffer layer, a collector layer on the sub-collector layer, a base layer on the collector layer, a wide-gap emitter layer on the base layer and a emitter contact layer on the emitter layer. The emitter layer extends the emitter contact layer, so the edge of the emitter layer is apart from the emitter contact layer and entirely covers the region where the collector layer and the sub-collector layer are overlapped to each other. According to this configuration, the transistor shows the enhanced reliability and the improved high frequency performance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a Hetero-Bipolar-Transistor (HBT) madeof III-V group compound semiconductors.

2. Related Prior Art

The HBT having a high current gain and an excellent high frequencyperformance is going to utilize as an amplifying device for an opticaltransceiver in high-speed optical communications. The reason HBT showssuch superior performance is that a semiconductor material is use in anemitter region, whose energy gap is wider than that used in a baseregion. Due to this wide gap emitter, a carrier injection into theemitter region can be maintained large even in the high carrierconcentration in the base region, thus shows the excellent highfrequency performance.

Although the HBT is an attractive device due to its high-speedcharacteristics and has improved mainly in this frequency performance,similar to other electron devices and optical devices, it is necessaryto pay attentions to not only the high-speed characteristics but alsoits reliability.

In conventional HBTs, several semiconductor layers are sequentiallygrown. A collector layer composed of InGaAs, a base layer composed ofInGaAs, and an emitter layer composed of InP are grown on the substratein this order. After the growth, several times of etchings of respectivelayer form an emitter mesa structure and a base mesa structure. Acollector electrode, a base electrode, and an emitter electrode areformed on the collector, the base, and the emitter, respectively. Thus,the HBT is completed.

In such conventional HBTs, a portion of the base layer, where theemitter mesa structure is formed thereon, operates as an intrinsic base.Since the emitter layer is formed just underneath the emitter mesastructure, side surfaces of the emitter layer are exposed to ambient.The edge of the interface between the emitter layer and the base layer,which is coincide with side surfaces of the emitter layer, is close tothe intrinsic base. Therefore, it is favorable for the reliability tolocate side surfaces of the emitter layer apart from the intrinsic baseregion.

SUMMARY OF THE INVENTION

The object of the present invention is to provide the new structure ofHBT with high reliability.

The device according to the present invention comprises a semiconductorsubstrate, a sub-collector layer on the substrate, a collector layer onthe sub-collector layer, a base layer made of InGaAs on the collectorlayer, an InP layer on the base layer, and an emitter contact layer madeof InGaAs on the emitter layer. The InP layer is provided within a firstregion on a primary surface of the substrate. The InGaAs emitter contactlayer is provided within a second region contained in the first region.Besides, the emitter contact layer is provided within a region where thesub-collector and the collector are overlapped to each other.

Since a projected area of the emitter contact layer upon the substrateis smaller than that of the InP layer, the portion of the InP layer justunderneath the emitter contact layer is able to behave as an intrinsicemitter. The configuration that the intrinsic emitter is apart from sidesurfaces of the InP layer enhances the reliability of the HBT.

On the second aspect of the present invention, the HBT comprises asubstrate, a sub-collector layer on the substrate, a collector layer onthe subcollector layer, an InGaAs base layer on the collector layer, anInP layer on the base layer, and an emitter contact layer on the InPlayer. The InP layer is provided within a first region on a primarysurface of the substrate, and the emitter contact layer is providedwithin the second region involved in the first region. The second regionincludes the portion where the collector layer and the sub-collectorlayer are overlapped to each other and regions surrounding theoverlapping portion.

Even in the configuration of the second aspect of the invention, sincethe effective emitter is formed in the region where the InGaAs emittercontact layer and the InP layer are overlapped to each other, theintrinsic emitter is apart from side edge of the InP layer, thusenhances the reliability.

When the sub-collector layer is formed in an island shape, inclinedsurfaces are exposed in the edge of the sub-collector layer. Thesemiconductor material grown onto such inclined surfaces shows differentetching endurance from those formed on the plane surface. Therefore, itis likely to be caused the defect, such as etching pit, whensemiconductor layers grown onto the inclined surface is soaked into theetching solution. According to the present invention, since the emittercontact layer covers such inclined surfaces, it is never exposed to theetchant, thus restrained from the creation of the defect and soprevented from deterioration.

The HBT of the present invention comprises a base electrode formed on aregion where the base layer and the InP layer are overlapped therein. Inthis configuration, since the InP layer extends under the baseelectrode, the intrinsic emitter region contacting to the emittercontact layer is enable to be apart from side surfaces of the InP layer.

It is favorable that the thickness of the InP layer is so as to makecarriers tunneling therethrough. In this configuration, the base currentflows from the base electrode to the base layer or from the base layerto the base electrode.

It is further favorable that the InGaAs emitter contact layer has theinverse mesa structure and the base electrode faces the side surfaces ofsuch inverse mesa structure of the emitter contact layer. The inversemesa structure has a form like a trapezoid, in which the lower side ofparallel lines is shorter than that of the higher side. Due to thisshape, an emitter electrode and a base electrode are obtainable throughthe self-aligned process. Since respective electrodes are electricallyisolated to each other while the distance between the electrodes isclose enough, the base resistance can be reduced, thus, enhances thehigh frequency performance.

Moreover, it is further favorable to form the sub-collector layer so asto have a normal mesa structure and to be covered with the collectorlayer.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1(A) shows a plane view of the first embodiment of the invention,FIG. 1(B) shows a cross sectional view along I—I in the FIG. 1(A), andFIG. 1(C) shows a cross sectional view along II—II in the FIG. 1(A);

FIG. 2(A) to FIG. 2(C) show the cross sectional view along [01-1] axisat the primary manufacturing step, while FIGS. 2(D) to 2(F) show crosssectional view along [011] axis of the first embodiment;

FIGS. 3(A) to 3(F) show the cross sectional view along [01-1] axis atthe primary manufacturing step following to FIGS. 2(A) to 2(C), whileFIGS. 3(D) to 3(F) show along [011] axis;

FIGS. 4(A) to 4(C) show the cross sectional view along [01-1] axis atprimary manufacturing steps following to FIGS. 3(A) to 3(C), while FIGS.4(D) to 4(F) show along [011] axis;

FIG. 5(A) shows the plane view of the second embodiment of the presentinvention, FIG. 5(B) shows a cross sectional view along I—I in the FIG.5(A), and FIG. 5(C) shows a cross sectional view along II—II in the FIG.5(A); and

FIG. 6(A) shows the plane view of the third embodiment of the presentinvention, FIG. 6(B) shows a cross sectional view along I—I in the FIG.6(A).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The favorable embodiments of the present invention will be described,especially the npn type bipolar transistor made of group III-V compoundsemiconductor materials. In the description, elements identical to eachother will be referred to with numerals identical to each other withouttheir overlapping explanations. In drawings, dimensions such as layerthickness of respective elements will not always reflect theirexplanation. Also, indices of crystal surface and crystal axis appearedin the description will contain their equivalent.

The First Embodiment

The first embodiment of the present invention will be explained. FIG.1(A) is a plane view of the first embodiment and FIG. 1(B) is asectional view along a line I—I in FIG. 1(A). Also, FIG. 1(C) is asectional view along a line II—II in FIG. 1(A). The line I—I and theline II—II are along [01-1] and [011] crystal axes, respectively, of thesemiconductor substrate that the HBT is formed thereon.

In FIG. 1(B), the HBT 1 has a semi-insulation InP substrate 2, a bufferlayer 30 on the (100) surface of the substrate 2, a sub-collector layer40 on the buffer layer 30, a collector layer 50 on the sub-collectorlayer 40, a base layer 60 on the collector layer 50, an emitter layer 70on the base layer 60, and the emitter contact layer 80 on the emitterlayer 70.

Furthermore, HBT 1 has a collector electrode 15 on the sub-collectorlayer 40 as shown in FIG. 1(C), a base electrode 16 on the emitter layer70 and an emitter electrode 18 on the emitter contact layer 80, as shownin FIG. 1(B). Conductive wiring are connected to the respectiveelectrodes, that is, wiring 25 on the collector electrode 15, wiring 26on the base electrodes 16, and wiring 28 on the emitter electrode 18.

The HBT 1 has insulating films (31, 32) to isolate respective electrodes(15, 16, and 18) and to protect semiconductor layers. The insulatingfilms are made of, for example, silicon nitride (Si₃N₄, herein afterdenoted as SiN).

The buffer layer 30 is made of un-doped In_(x)Ga_(1−x)As and itsthickness from 300 nm to 500 nm. The sub-collector layer 40 is n-typeIn_(x)Ga_(1−x)As with thickness from 300 nm to 500 nm. As shown infigures from 1(A) to 1(c), the sub-collector layer 40 is formed assubstantially rectangle shape with its long side along the [011] axis ofthe substrate. Moreover, side surfaces of the sub-collector layer 40 areformed as normal mesa structures as shown in FIGS. 1(B) and 1(C). Thesub-collector 40 is doped with Si and its electron concentration has arange from 0.5×10¹⁹ to 2.0×10¹⁹ (cm⁻³).

The collector layer 50 is an n-type In_(x)Ga_(1−x)As with its thicknessfrom 300 nm to 500 nm The collector layer 50 is formed as substantiallyrectangle shape with its long side along [011] axis and the other sidealong [01-1] axis. The collector layer 50 is doped with Si and itselectron concentration is the range from 1.0×10¹⁶ to 5.0×10¹⁶ (cm⁻³).The base layer 60 is p-type In_(x)Ga_(1−x)As with a thickness of about50 nm. The base layer 60 is doped with Zn or C, and hole concentrationfrom 1.0×10¹⁹ to 3.0×10¹⁹ (cm⁻³).

The emitter layer 70 is an n-type InP with thickness of about 10 nm. Theemitter layer 70 has the identical plane shape with that of the baselayer 60. The emitter layer 70 is doped with Si and the electronconcentration is 4.0×10¹⁸ (cm⁻³). The favorable thickness of the layer70 is from 5 nm to 20 nm, since the function of the emitter layer isfailed below 5 nm while the current tunneling through the emitter layer70 will be hard over 20 nm, which leads the inferior performance of thetransistor.

The emitter contact layer 80 is an n-type In_(x)Ga_(1−x)As and formed soas to be contained the sub-collector layer 40 therein. The layer 80 hasside surfaces formed along the [011] axis, which show reverse mesastructures. The thickness of the layer 80 is about 250 nm. The carrierconcentration of the layer 80 is divided into two regions. One is formedwithin about 50 nm from the interface to the emitter layer 70 and theelectron concentration is about 5.0×10¹⁸ (cm⁻³), while the other isformed on the former region and the electron concentration is about2.0×10¹⁹ (cm⁻³) larger than that of the former region. The reason todivide the emitter contact layer 80 into two layers is to realize thesmall contact resistance between the emitter electrode 18 and theemitter contact layer 80.

The base layer 60, collector layer 50, and sub-collector layer 40 aremade of In_(x)Ga_(1−x)As and the constitutions of In or Ga are soselected to match the lattice constant of the layers to the InPsubstrate, in which x equals to 0.53. The lattice matching means thedifference of the lattice constant between layers of In_(x)Ga_(1−x)Asand the InP substrate is within ±0.1%.

As shown in FIG. 1(C), the collector electrode 15 is formed on thesub-collector layer 40, while the base electrode 16 is formed on theemitter layer 70 apart from the emitter contact layer 80 and facing theone side of the emitter contact layer 80. The emitter electrode 18 isformed on the emitter contact layer 80. The respective electrodes aremade of Titanium (Ti), Platinum (Pt), and Gold (Au) successfullydeposited in this order. A number of conductive wiring made of, forexample Aluminum (Al), is connected to respective electrodes. Since thecross sectional shape of the sub-collector layer 40 has normal mesastructures, the base electrode 16 is bent by obtuse angle at the edge ofthe sub-collector layer and the stress applied to the base electrode 16is be reduced.

Next will be described the operation of the HBT 1. Assuming theconfiguration of the emitter grounding, the current flows from the baseelectrode 16 to the emitter electrode 18 by the bias potential appliedbetween the electrodes. The injected carriers from the base electrode 18penetrates to the base layer 60 through the emitter layer 70 is conveyedin the base layer 60 to the region where the emitter contact layer 80 isformed, and reaches the emitter electrode 18 through the emitter layer70 by tunneling and conveyed in the emitter contact layer 80.

The current from the collector electrode 15 to the emitter electrode 18flows concurrently with the current from the base electrode 16 to theemitter electrode 18. The injected current from the collector electrode15 flows in the sub-collector layer 40, the collector layer 50, the baselayer 60, the emitter layer 70 by tunneling, and the emitter contactlayer 80.

Since the electron concentration in the sub-collector layer 40 is largerthan that of the collector layer 50 by three orders or higher in thepresent embodiment, the current penetrates from the sub-collector layer40 to the collector layer 50 through entire interface between thelayers. The current into the collector layer penetrates to the baselaser 60, namely, the region where the current flows in the collectorlayer 50 provides the function of current amplification. In other words,the sub-collector layer 40 decides the intrinsic collector region in thecollector layer 50.

The current from the collector layer 50 to the emitter contact layer 80flows from the intrinsic collector region to the emitter contact layer80 through the base layer 60 and the emitter layer 70. The regions wherethe current flows operate as an intrinsic emitter region and anintrinsic base region. The portion of the emitter layer 70 where thebase electrode is formed does not provide a function of the intrinsicemitter region but shows a current flow pass from the base electrode 16to the emitter electrode 18.

Next is the improvement of the HBT 1. The primary feature of the HBT 1is derived from the emitter contact layer 80 being formed smaller thanthe emitter layer 70 and only the region within the emitter layer 70opposing to the emitter contact layer 80 shows the intrinsic emitterregion. That is, the intrinsic emitter region is apart from the edge ofthe emitter layer 70.

When the intrinsic emitter region is formed by the etching of theemitter layer 70 and has the same area with the emitter contact region80 like conventional HBTs, edges of the emitter layer 70 are exposed tothe ambience. In such a configuration, these edges are treated invarious processes. This leads to the less reliability. However, in thepresent embodiment, though the emitter layer 70 has the same area withthe base layer 60, edges of the emitter layer 70 are apart from theintrinsic emitter region. This leads the high reliability of the presentHBT.

Furthermore, the base layer 60 is covered by the emitter layer 70 andprotected from the extrinsic contamination. When the surface of the baselayer 60 is exposed to the ambience, the various surface states would becreated and increase the surface leak current due to the presence of thesurface states. In the present embodiment, the base layer 60 is whollycovered by the emitter layer 70 and the emitter layer 70 is grownsequentially on the base layer 60, the surface states in the base layer60 can be reduced and thus the leak current. Since the thickness of theemitter layer is so thin, the base electrode 16 can be formed directlyonto the emitter layer 70.

Another advantage of the HBT 1 is the improvement of the high frequencyperformance because of the reduction of the capacitance between the baseelectrode and the collector electrode. Since the sub-collector 40 iscovered by the collector layer 50 in the region where the base electrodeis formed, the capacitance between electrodes can be reduced. Typicalhigh frequency characteristics according to the present HBT show thecut-off frequency f_(T) over 120 GHz (@ 20 mA collector current), themaximum oscillation frequency f_(MAX) over 90 GHz (@ 5 mA collectorcurrent).

Next is an explanation of the manufacturing process of the HBT 1. FromFIG. 2(A) to FIG. 2(F), from FIGS. 3(A) to 3(F), and from FIGS. 4(A) to4(F) show the cross sectional view of the HBT at each process steps.From FIGS. 2(A) to 2(C), from FIGS. 3(A) to 3(C), and from FIGS. 4(A) to4(C) show the cross sectional view of the HBT along the [01-1] axis ofthe semiconductor substrate. Further, the cross sectional views alongthe [011] axis are shown in figures from 2(D) to 2(F), from 3(D) to 3(F)and 4(D) to 4(F). Pairs of FIG. 2(A) and 2(D), FIG. 2(B) and 2(E), FIG.2(C) and 2(F) show views at the same process step. Also, figures from3(A) to 3(A) and figures from 4(A) to 4(F) show views at same processsteps, respectively.

The manufacturing method of the HBT of the first embodiment previouslyshown is divided roughly into three steps. That is, a sub-collectorformation step, various mesa formation steps, and an electrode formationstep. These steps are processed sequentially.

An epitaxial growth of semiconductors at the sub-collector formationstep and the various mesa formation step are executed by the MOCVD(Metal Organized Chemical Vapor Deposition) technology. In the MOCVD,various sources can be utilized, such as the tri-methyl-Indium as anindium source, the tri-ethyl-Gallium as a gallium source, the hydrogenArsenide for an arsenic source and the hydrogen Phosphate forphosphorous source. The silane (SiH₄) is used for the n-type dopantsource, while the di-ethyle-Zinc for the p-type dopant source. In thecase of carbon doping, carbon bromide is used.

Semiconductor layers with predetermined atomic concentrations andcarrier concentrations can be obtained by supplying appropriate sourcesinto the reaction chamber of the MOCVD equipment. Reaction temperaturesbetween 600° C. and 750° C. are favorable. The quality of the obtainedsemiconductor layer will be poor in temperatures out of above range.

The formation of the sub-collector layer in which the sub-collector mesaregion is provided will be described. This process is divided into twosteps, one is the epitaxial growth of the semiconductor layer and theother is the etching of the grown layer.

First, as shown in FIGS. 2(A) and 2(D), the buffer material 3 and thesub-collector material 4 are sequentially grown on the (100) surface ofthe semi-insulating InP substrate 2. The sub-collector material 4 ismade of n-type In_(x)Ga_(1−x)As with a thickness from 300 nm to 500 nmand doped with Si. The electron concentration in the sub-collectormaterial is about 1.0×10¹⁹ (cm⁻³). This sub-collector material will beprocessed to the sub-collector layer 40.

Next, an etching mask made of photo resist is patterned on thesub-collector material 4 by the photolithography. The etching maskshapes nearly rectangle with its one side along [011] axis of thesubstrate. The prescribed sub-collector layer 40 is obtained by theusing this patterned photo resist as an etching mask.

An etchant is the mixture of a sulfuric acid (H₂SO₄), a hydrogenperoxide (H₂O₂) and a water (H₂O). By using this mixture as an etchant,every side surfaces of the sub-collector layer 40 form normal mesastructure as shown in FIG. 2(B) and FIG. 2(E). The etching amountdepends on the etching time, which is determined by the pre-experiment.It is favorable to etch the upper portion of the buffer material 3 byabout 100 nm, since the portion to be removed within the sub-collectormaterial 4 will be reliably taken off. After removing the photo resistwith a solvent, the step for producing the subcollector layer 40 iscompleted.

The collector layer, the base layer and the emitter layer are formed by(1) the epitaxial growth of respective materials, (2) the etching of theemitter contact layer, and (3) the forming of a mesa where the emitterlayer, the base layer and the collector layer are involved.

The InP substrate 2, which the sub-collector layer is formed thereon, isloaded within the reaction chamber of the MOCVD equipment. The collectormaterial 5, the base material 6, the emitter material 7, and the emittercontact material 8 are grown epitaxially sequentially as shown in FIG.2(c) and 2(F). In the growth, sources containing dopant materials arealso supplied to secure predetermined carrier concentrations of theelectron and the hole.

The emitter contact material 8 is made of an n-type In_(x)Ga_(1−x)As andis converted to the emitter contact layer 80 in the later process. Thethickness of the emitter contact material is about 250 nm. The layer 8is divided into two portions by its carrier concentration. The lowerregion is within about 50 nm from the interface to the emitter material7 and has the electron concentration of about 1.0×10¹⁸ (cm⁻³). The upperregion is on the lower portion and has the electron concentration ofabout 2.0×10¹⁹ (cm⁻³). To form such two regions, the supply amount ofthe silane (SiH₄), which is an n-type dopant, is favorable to change bystep-like function. These epitaxial growths of respective materials areshown in FIG. 2(C) and 2(F).

The emitter contact layer 80 is formed as described below. First, aphoto resist is patterned on the emitter contact material 8. This photoresist functions as an etching mask and shapes a rectangular with itsone side being along [011] axis of the substrate.

After the formation of the etching mask by photo resist, the InPsubstrate 2 is dipped into an etchant of the mixture of the phosphoricacid (H₃PO₄), Hydrogen peroxide (H₂O₂), and water (H₂O) with its mixtureratio of H₃PO₄:H₂O₂:H₂O=5:1:10. This etchant shows the selective etchingcharacteristics of the InGaAs to the InP. The etching rate for the InPemitter material 7 is enough small compared to the InGaAs emittercontact material 8. Therefore, the etching will substantially stop afterthe exposing of the emitter material 7. One alternative method is to usethe non-selective etchant such as the mixture of the sulfuric acid,hydrogen peroxide and water. In the latter case, the etching amount mustbe determined through a pre-experiment.

After removing of the photo resist by the organic solvent, the emittercontact layer 80 is completed, as shown in FIG. 3(A) and FIG. 3(D). Thecross sectional shape of the emitter contact layer 80 appears, as shownin FIG. 3(A), an inverse mesa structure at the side edge extending alongthe [011], while a normal mesa structure along the [01-1] axis as shownin FIG. 3(D).

Next, another mesa is formed, which contains the emitter material 7, thebase material 6, the collector material 5 and the buffer material 3.After the deposition of photo resist pattern on the emitter material 7,which completely to cover the emitter contact layer 80 and shapes nearlyrectangular with one side edge extending along the [011] axis of thesubstrate, two step etchings are executed. First, a portion not coveredby the photo resist of the emitter material 7 is removed by the mixtureetchant of hydrochloric acid (HCl) and water. Since this mixture shows aselective etching characteristic of the InP to the In_(x)Ga_(1−x)As, theIn_(x)Ga_(1−x)As under the InP emitter material 8 is hard to be etched.The emitter layer 70 is obtained by this first etching. Then, the basematerial 7, the collector material 6 and the buffer material 3, all madeof In_(x)Ga_(1×x)As, are etched by the mixture of the sulfuric acid(H₂SO₄), hydrogen peroxide (H₂O₂), and water (H₂O)=1:1:500. Since thisetchant also shows the selective etching characteristics of theIn_(x)Ga_(1×x)As to the InP, the InP substrate is hard to remove afterthe completion of the etching of the In_(x)Ga_(1×x)As material. Afterthe second lo etching, the base layer 70, the collector layer 60, andthe buffer layer 30 with predetermined shape are obtained and the mesaregion 10 containing layers from 30 to 80 is formed as shown in FIGS.3(B) and FIG. 3(E).

The primary portion of the HBT is in this mesa region 10 formed throughseveral times of the etching and a region surrounding the mesa regionexposes the InP substrate 2. This means that respective HBTs formed onthe semi-insulating substrate 2 will be electrically isolated with eachother. Thus, the formation step of the mesa region 10 is implicitlyequivalent to the device isolation step.

After the completion of mesa region, electrodes are formed. First, thebase electrode 16 and the emitter electrode 18 are made by theself-aligned process. A SiN film 31 is deposited by CVD (Chemical VaporDeposition) technique on the whole substrate 2. After deposition, anetching mask made of photo resist is patterned onto the SiN film 31. Themask has a predetermined shape to expose the portion of the emittercontact layer 80 and the emitter layer 70. The portion of the insulatingfilm not covered by the photo resist is removed by the RIE (Reactive IonEtching) and the emitter contact layer 80 and the emitter layer 70 areexposed.

Next, two electrodes (16, 18) are formed by Lift-Off process. After theRIE processing, titanium (Ti), platinum (Pt), and gold (Au) aresequentially deposited in the opening region of the photo resist andalso onto the photo resist. Since edges along the [011] axis of theemitter contact layer has the inverse mesa structure, metal materialscan not be deposited on the emitter layer 70 just under the eaves of theemitter contact layer 80. Therefore, it is able to separate completelythe base electrode from the emitter electrode. By using suchself-aligned process, two electrodes can be simply obtainable. Moreover,since the self-aligned process is enable to close the base electrode tothe intrinsic emitter region, which results on the reduction of the baseresistance, the high frequency performance of the HBT will be improved.

By dissolving the photo resist using, for example, acetonic solvent, themetal film left on the photo resist can be removed, the emitterelectrode 18 and the base electrode 16 are completed, as shown in FIG.3(C) and FIG. 3(F). Thermal treatment for one minute under thetemperature of 400° C. in the nitrogen ambient makes an ohmic contact torespective semiconductor layers.

Next, a photo resist is patterned so as to make an opening where thecollector electrode is formed. The emitter layer 70, the base layer 60,and the collector layer 50 within the opening are removed by the mixtureof H₂SO₄: H₂O₂:H₂O=1:1:500 following the etching of the SiN film by theRIE technique. After the RIE etching, the sub-collector layer 40 isexposed within the opening. The collector electrode 15 is formed by theLift-Off method. Titanium, Platinum, and gold are sequentially depositedon the sub-collector layer 40 within the opening and also onto the photoresist. By dissolving the resist, metals left on the resist are removed.Finally, the collector electrode is completed as shown in FIG. 4(A) andFIG. 4(D).

Following to the electrode formation, an insulating film 32 such as SiNis deposited so as to cover the respective electrodes (15, 16, and 18)by the CVD technique. The multi-layered mask made of photo resist,Silica and photo resist is formed on the insulating film 32 andpatterned so as to make openings where the wiring 25 connecting to thecollector electrode 15 and the wiring 26 to the base electrode 16 areformed. After the patterning of the resist, via holes for wiring 25 and26 to the respective electrodes are formed and wiring metal such asaluminum are deposited within the opening and onto the resist. Bydissolving the resist with organic solvent, metals left on the resistare removed and the wiring 25 and 26 are completed as shown in FIG. 4(B)and FIG. 4(E).

Similar process with the wiring for the collector electrode 15 and thebase electrode 16 is applied for the wiring 28 for the emitter electrode18 as shown in FIG. 4(C) and FIG. 4(F). Finally, the HBT 1 is obtainedthrough thus described process.

Second Embodiment

The second embodiment of the present invention will be described. TheHBT 100 according to the second embodiment has the same feature as thefirst embodiment without the configuration of the emitter contact layer,the emitter electrode on the emitter contact layer and the baseelectrode. The manufacturing process of the second embodiment has thesame feature with the first embodiment without the configuration of theetching mask for the emitter contact layer. Only the difference betweentwo embodiments will be described.

FIG. 5(A) shows a plane view of the second embodiment of the present HBT100. FIG. 5(B) is a cross sectional view along a I—I line in the FIG.5(A), while FIG. 5(C) shows a cross sectional view along a II—II line inthe FIG. 5(A). The I—I line and the II—II line in the FIG. 5(A)corresponds to the lines along [011] axis and the [01-1] axis of thesemiconductor substrate, respectively.

As shown in figures from 5(A) to 5(C), the area of the emitter contactlayer 81 is larger than that of the sub-collector layer 40 in the thisembodiment. Moreover, the emitter contact layer 81 covers nearly wholearea of the sub-collector layer 40. Even in this configuration, theintrinsic emitter, which functions as the emitter, is restricted to theregion directly contact to the emitter contact layer 81. Since sidesurfaces of the emitter layer 70 are apart from the intrinsic emitterregion, the reliability of the HBT of the second embodiment is enhanced.

The second embodiment has another advantages described below. Theemitter contact layer 81 covers nearly whole area of the sub-collectorlayer 40, in other words, the emitter contact layer 81 covers not onlythe region where the sub-collector layer 40 overlaps the collector layer50 but the portion surrounding this overlapping region. There are someside surfaces reflecting the mesa structure of the collector layer 50.Since the semiconductor material grown on such side surfaces, which isinclined, shows different etching characteristics from that formed onthe plane surface, it is likely to be caused the defect such as etchingpit when such side surface is soaked in the etching solution. In thepresent HBT 100, since side surfaces are covered by the emitter contactlayer 81, it is never exposed to the etchant, restrained from thecreation of the defect and thus prevented from deterioration.

Furthermore, since the emitter layer 70 covers the base layer 60, thesurface states in the base layer 60 is reduced, and so does the leakcurrent.

The Third Embodiment

Next is the explanation of the third embodiment of the presentinvention. The HBT 101 of the third embodiment has the same feature withthe first embodiment except that the base electrode 16 directly contactsto the base layer 60. Also, the manufacturing process has the samefeature with that of the first embodiment except that a portion of theemitter layer 70 is removed just before the base electrode formation.Only the difference will be described below.

FIG. 6(B) shows a cross sectional view of the third embodiment along theline I—I in the FIG. 6(A), which corresponds to the [01-1] axis of thesubstrate.

As shown in the FIG. 6(B), the portion of the emitter layer is removedand the base electrode 16 is formed thereof. Even in such configuration,since edges of the emitter layer are apart from the region where theemitter contact layer 80 and the emitter layer 70 are interfaced, thereliability can be secured as in the case of the first embodiment. Onetypical example to form such structure is that the portion of theemitter layer 70 is removed by Reactive Ion Etching (RIE) just beforethe base electrode 16 formation. In the RIE, only the portion of theemitter layer 70 where the base electrode is formed thereof can beremoved under the condition that the region of the emitter layer justunderneath the overhang of the emitter contact layer 80 is notinfluenced by the RIE process. Various gas sources are available for theetching of the emitter layer 70, such as a mixing of CH4/H2/Ar, HI/Cl₂,BCl₃/Cl₂ and HBr/Cl₂.

In the present HBT 101, since the base electrode 16 directly contacts tothe base layer 60 with a high carrier concentration not through theemitter layer 70 as in the previous embodiment, it is able to make ancontact resistance to be enough low.

Still further advantage in the present embodiment is that thesub-collector layer 40 is entirely covered by the collector layer 50,which leads the reduction of the capacitance between the base layer 60and the sub-collector layer 40. Thus, the high frequency performance ofthe HBT 101 is enhanced.

The present invention is not restricted to embodiments above describedand can be modified in various manners.

It is favorable that the width of the sub-collector layer 40 is nearlyequal to that of the emitter contact layer 80, although it isillustrated as the former is wider than the latter in FIGS. 1(B), from2(A) to 2(C), from 3(A) to 3(C) and from 4(A) to 4(C). When the width ofthe both layers are nearly equal, the current flowing from the collectorto the emitter is defined by the width, consequently the width of theintrinsic emitter is also defined. Moreover, the intrinsic emitter isenough apart from the edge of the emitter layer 70.

Moreover, although the base electrode and the emitter electrode areformed simultaneously while the collector electrode is formed in anotherprocess step in embodiments above mentioned, it is able to make allelectrodes in the same time. Although the photo resist is used as anetching mask to form various mesa region, a SiN film with a etchingpattern thereof instead of the photo resist is also available as themask to make mesa regions.

As described above, the emitter contact layer made of In_(x)Ga_(1×x)Asis formed so as to be smaller than the InP layer thereunder. The portionof the InP layer that contacts to the In_(x)Ga_(1−x)As layer operates asthe intrinsic emitter. The intrinsic emitter is apart from edge of theInP layer. Thus, the HBT with further reliability can be provided.

From the invention thus described, it will be obvious that theembodiments may be varied in many ways. Such variations are not to beregarded as a departure from the spirit and scope of the invention, andall such modifications as would be obvious to one skilled in the art areintended for inclusion within the scope of the following claims.

What is claimed is:
 1. A bipolar transistor, comprising: (a) asemiconductor substrate; (b) a sub-collector layer on said substrate;(c) a collector layer on said sub-collector layer; (d) a base layer onsaid collector layer and made of InGaAs; (e) an emitter layer made ofInP on said base layer, said emitter layer being provided in a firstregion of said substrate; and (f) an emitter contact layer made ofInGaAs on said emitter layer, said emitter contact layer being providedin a second region of said substrate, said first region involving saidsecond region therein, wherein said emitter contact layer is formed in aregion where said collector layer and said sub-collector layer areoverlapped to each other.
 2. The bipolar transistor according to theclaim 1, further comprises a base electrode provided in a region wheresaid base layer and said emitter layer are overlapped to each other,said emitter layer being sandwiched by said base electrode and said baselayer.
 3. The bipolar transistor according to the claim 2, wherein saidbase electrode directly contacts to said base layer.
 4. The bipolartransistor according to the claim 1, wherein said emitter layer has athickness to enable to tunnel carriers from said base electrode to saidbase layer.
 5. The bipolar transistor according to claim 1, wherein saidemitter contact layer has at least a pair of side surfaces having aninverse mesa structure.
 6. The bipolar transistor according to claim 5,wherein said base electrode faces at least one of said side surfaces ofsaid emitter contact layer.
 7. The bipolar transistor according to claim1, wherein side surfaces of said sub-collector layer have normal mesastructures.
 8. A bipolar transistor operated by base injected carriers,comprising: (a) a semiconductor substrate; (b) a sub-collector layer onsaid substrate; (c) a collector layer on said sub-collector layer; (d) abase layer made of InGaAs on said collector layer; (e) an emitter layermade of InP on said base layer, said emitter layer being provided in afirst region of said substrate; and (f) an emitter contact layer made ofInGaAs on said emitter layer, said emitter contact layer being providedin a second region of said substrate, said first region involving saidsecond region therein, wherein said second region contains a regionwhere said collector layer and said sub-collector layer are overlappedto each other.
 9. The bipolar transistor according to claim 8, furthercomprises a base electrode provided in a region where said base layerand said emitter layer are overlapped to each other, said emitter layerbeing sandwiched by said base electrode and said base layer.
 10. Thebipolar transistor according to claim 9, wherein said base electrodedirectly contacts to said base layer.
 11. The bipolar transistoraccording to the claim 8, wherein said emitter layer has a thickness toenable to tunnel carriers from said base electrode to said base layer.12. The bipolar transistor according to claim 11, wherein said baseelectrode faces at least one of said side surfaces having inverse mesastructures.
 13. The bipolar transistor according to claim 8, whereinsaid emitter contact layer has a pair of side surfaces having inversemesa structures.
 14. The bipolar transistor according to claim 8,wherein entire side surfaces of said sub-collector layer have normalmesa structures.